The present invention relates to data signal demodulators and, more particularly, to a novel improved data demodulator utilizing a comparative decision circuit and having an easily-varied operating frequency and data bit rate range.
Digital data is commonly sent over a communications channel by shifting the frequency of a transmitted communications signal between discrete values representing the digital information. For binary digital data, the carrier frequency is typically shifted to a high frequency for transmitting a first binary value and to a lower frequency for transmitting the remaining binary value. A data receiver receives this frequency-shifted-keyed (FSK) carrier and decides whether the higher or lower frequency is then being received to provide a data output having the first or second binary value. While many such data demodulator circuits are known to the prior art, not all of these circuits are capable of being monolithically integrated into a single, low-cost integrated circuit component. It is highly desirable that any such integrated component have the ability to shift the operating frequency band by merely changing a reference frequency; one such demodulator is described and claimed in my co-pending application Ser. No. 409,237 filed Aug. 18, 1982, now U.S. Pat. No. 4,475,219 issued Oct. 2, 1984, assigned to the assignee of the present application and incorporated herein in its entirety by reference. Briefly, the absolute-value-decision FSK demodulator circuit of the aforementioned application utilizes means for providing first and second local reference signals, in phase-quadrature to one another, with each of the local reference signals being coupled to an associated one of a pair of signal mixing means, each receiving a hard-limited version of the received signal to be demodulated. The difference outputs of one mixing means are provided to a counter, which is reset at the start of each bit timing interval. The count in each of a pair of counters is clocked by one output of the other mixing means, such that the absolute portion of the time that the input signal is at one or the other of the FSK frequencies can be used to provide the binary data output condition at the end of the bit time interval. In such a digital data demodulator, the arithmetic mean of the FSK frequencies is supplied to the phase-quadrature local reference signal means and can be easily varied to vary the frequency of the FSK channel being received.
It is highly desirable that a comparative, rather than an absolute, value decision process be utilized in such a detector, to allow the detector to be utilized for receiving digital data which is transmitted as a more-reliable encoded signal, e.g. as either Manchester-encoded FSK signals or frequency-chirped (sweep up/sweep down) frequency-modulated signals.